1. Technical Field
The present invention relates to a burn-in testing device and method, and more particularly, to a memory device having an open bit line cell structure that uses a wafer burn-in testing scheme and a method for testing the same.
2. Discussion of Related Art
Wafer burn-in (WBI) testing performed on a wafer has been widely used as a method for screening weak cells in a semiconductor memory device. In the WBI testing method, a high operation voltage is generally applied at a high temperature. To shorten test time, a number of word lines in each memory block are simultaneously activated. Subsequently, data is written to a plurality of memory cells and sensed in a certain time. As such, to screen the weak cells, stress is applied to the memory cells.
FIG. 1 illustrates a typical folded bit-line cell structure. In a conventional WBI test, a write operation begins by simultaneously activating even word lines WL0 and WL2 or odd word lines WL1 and WL3 of word lines in memory blocks 110 and 120. A desired voltage is then applied to an external pad so that a voltage VBL is applied and written to all cells in the memory blocks via a voltage equalizing circuit 140.
Further, in a sensing operation subsequent to the write operation for the WBI test, all the word lines in the memory block are simultaneously activated and a sensing enable signal PSE is applied to a sense amplifier 130. The sense amplifier amplifies and senses a voltage difference between a pair of bit lines to screen for defects of bridges between the bit line pairs. The WBI test is disclosed in Korean Patent No. 281900 and U.S. Pat. No. 6,259,638.
FIG. 2 illustrates a typical memory device having an open bit-line cell structure. Bit lines BL and inverted bit lines /BL extend to both sides of a sense amplifier 230. Memory cells are formed at intersection regions of the bit lines and word lines.
When the same WBI write method as that in the folded bit line structure shown in FIG. 1 is applied to the memory device of FIG. 2, e.g., when first word line WL0 and third word line WL2 in memory blocks 210 and 220 are simultaneously activated, and then, an external voltage VBL is applied and written to memory cells via a voltage equalizing circuit 240, only the same voltage (data) is always written to the memory cells which are connected to the first and third word lines WL0 and WL2 via the bit lines and the inverted bit lines.
Because the same voltage (data) is written to memory cells upon activating all word lines and then applying a sensing enable signal PSE to carry out WBI sensing operation after the write operation is completed, a voltage difference is not generated between the bit line and the inverted bit line. Consequently, sensing operation is not performed and in turn defects of bridges between the bit lines cannot be screened.
Accordingly, a need remains for a method for burn-in test directed to a memory device having an open bit line cell structure.